As is known to those skilled in the semiconductor art, transistors are the main building blocks of integrated circuits (ICs). Modem ICs interconnect millions of densely configured transistors that perform a wide variety of functions. To achieve this densely packed configuration, the physical dimensions of the transistors are typically scaled down to the sub-micron regime. Generally, the transistors used in the sub-micron regime typically include a polysilicon gate. However, polysilicon gates may suffer device performance degradation due to a polysilicon depletion effect in which an electric field applied to a polysilicon gate removes carriers (holes in a p-type doped polysilicon, or electrons in an n-type doped polysilicon) so as to create a depletion of carriers in the area of the polysilicon gate near the underlying gate dielectric of the transistor. This depletion effect results in a reduction in the strength of the electric field at the surface of the CMOS device when a voltage is applied to the polysilicon gate electrode, which can have an adverse affect on the transistor performance.
One proposed way of improving the performance of sub-micron transistors is to use metal gates in place of conventional polysilicon gates. While replacing traditional polysilicon gates with metal or metal alloy gate electrodes eliminates the polysilicon depletion effect, there are still problems associated with the use of such metal gates. One problem encountered is that the carriers from the metal gate can diffuse into the underlying gate dielectric material, thus causing shorting of the device.
Another problem encountered with the use of metal gates is workfunction mismatch, wherein the workfunctions of the metal gate p-channel transistor and the metal gate n-channel transistor do not match the workfunctions of the p- and n-channel transistors of the polysilicon gate. It is well-known that in CMOS devices, there are generally two different types of gate electrodes, an n-channel gate electrode and a p-channel gate electrode, which have two different workfunction values (i.e., an energy level of a semiconductor which can be near the valence or the conduction band of the material). The workfunction values are typically about 4.1 and 5.2 electron volts (eV) for the n-and p-channel electrodes respectively, and the values are generally formed by doping the polysilicon to be either n- or p-type.
In contrast, previously proposed metal gate electrodes have focused on using one type of metal for both channels of the gate electrode, with a workfunction that is located in the middle of the p- and n-channel workfunction range (e.g., about 4.7 eV). A drawback to this mid-gap workfunction approach is that this type of metal gate device cannot easily achieve a desirable small threshold voltage, which is the amount of voltage that determines the transistor's ‘on’ and ‘off’ states, without causing degradation in device performance.
Low workfunction metal gates, which have a workfunction below the mid-gap range, i.e., less than 4.2 eV, are required for dual metal CMOS to substitute for n+ polysilicon gates that are currently being used in conventional CMOS transistors. Likewise, high workfunction metal gates, which have a workfunction above the mid-gap range, i.e., greater than 4.9 eV, are needed as a substitute for p+ polysilicon gates. Well-known band edge n-field effect transistor (FET) metal gates (including metals such as, for example, Ti, V and Zr) with low workfunctions are inherently not stable after going though standard high temperature self-aligned CMOS processes. By “high temperature”, it is meant a temperature of about 550° C. or greater.
Due to this inadequate thermal stability of low workfunction metals, there is a need for providing a CMOS structure having a gate stack that can be used to achieve both nFET and pFET workfunctions.